Just worked out it's because I had AVX512 disabled. When enabled L1 cache scores are back in the 4.5-5k range.
I've settled on 54/52, but using a +1 bin for all core only - so if TVB feels inclined, it can boost all core to 53. This way max possible clocks are 54 2c/53 all core.
As for IPC, crack that 750 ST Adam