leaked bulldozer/Llano performance relative to SB

[Sasquach]

http://www.donanimhaber.com/islemci/...-sonuclari.htm

Anyone speak turkish? I found the link on techreport.

The slides indicate that for Llano, the CPU side will get destroyed by SB (this is obvious) and the GPU performance will make up for the overall score when both the CPU and GPU are taken into consideration (the GPU being superior to SB's is also obvious).

Bulldozer is shown to just edge out the SB i7-2600k, so i think thats good news on that front. But it seems like AMD is calling their BD parts 8core units when its really more of in between fake cores (hyperthreading) and real cores. I guess technically it does count as real cores. (its a 4 module unit)

[caveman-jim]

Originally Posted by Sasquach

But it seems like AMD is calling their BD parts 8core units when its really more of in between fake cores (hyperthreading) and real cores. I guess technically it does count as real cores. (its a 4 module unit)

It can execute 2 int threads and 2 fp threads in each module, hence it is a dual core. What is different is being able to combine the fp to work on one thread for more throughput for an fp intensive task instead of leaving 1 fp idle.

Read more here.

[lumpyhed]

link appears to be dead for me good news if its credible though! a real bang for the buck system by the sounds of it

[BababooeyHTJ]

Originally Posted by caveman-jim

It can execute 2 int threads and 2 fp threads in each module, hence it is a dual core. What is different is being able to combine the fp to work on one thread for more throughput for an fp intensive task instead of leaving 1 fp idle.

Read more here.

I didn't know that. Thanks for the link.

[FX-Overclocking]

I HATE these comparisons where they do a 3Dmark and compare one CPU paired with a nice videocard to an Intel paired with a ??? and then show the AMD with 2x the FPS. Well duh! That's redonkulious... show a photoshop or video rendering benchmark with both cards running the SAME GPU if you wanna compare CPUs.

[Sasquach]

Originally Posted by FX-Overclocking

I HATE these comparisons where they do a 3Dmark and compare one CPU paired with a nice videocard to an Intel paired with a ??? and then show the AMD with 2x the FPS. Well duh! That's redonkulious... show a photoshop or video rendering benchmark with both cards running the SAME GPU if you wanna compare CPUs.

Im under the impression that all SB CPU's have onchip graphics. So im guessing the benches are taking the SB CPU + SB HD graphics. In the case of BD, its a CPU only and only the Fusion APU's have the onchip Radeon graphics. I suppose they threw in the 6670 because its not that expensive and supposedly would be a midrange GPU better matched to a CPU (as opposed to a low range GPU which would be a waste paired with a high end CPU)

[moshpit]

Originally Posted by caveman-jim

It can execute 2 int threads and 2 fp threads in each module, hence it is a dual core. What is different is being able to combine the fp to work on one thread for more throughput for an fp intensive task instead of leaving 1 fp idle.

Read more here.

Wait a minute, I thought it could only execute one FPU in per module on any clock cycle, that it's also NOT true dual cores within each module but is a hybrid SMT/SMP approach called CMP (Cluster Multi-Processors) and some resources are still shared on each module between the units. In fact, Ars Technica said they felt it would execute closer to 1.8 threads per clock versus Intel's HT which only does 1.2 per clock.

http://arstechnica.com/business/news...-bulldozer.ars

AMD claims that a single Bulldozer core can execute two threads like a 1.8-core part, on average, which strikes me as a bit optimistic. But again, these numbers will be very highly workload dependent. What isn't in doubt is that Bulldozer will perform much better than a regular SMT design, but at the cost of a ton of additional, very power-hungry integer execution hardware. Whether and how often that tradeoff works to Bulldozer's advantage will depend greatly on the performance and tuning of Bulldozer's cache hierarchy, on whether the core's internal buffers and queues are correctly sized, and on how efficiently and fairly space in those queues is allocated to each thread (especially in cases where one or both threads are greedy and are overusing shared resources).

In fact, each module only contains a single, shared double wide FPU and 2 INT units, so only 2 INT or 1 INT + 1 FPU can be executed simultaneously, but never all 3 units at same time, and never more then 2 threads on any one module, AND, never the FULL 2 threads except in the MOST optimized scenarios and even then falling short of the full "2x" rate and more of a "1.8" rate of thread processing.

A 4 module unit will not equal a true 8 core CPU, thought it's looking more and more likely AMD is going to try to spin that if current hype is to be believed. It will fall short, though will do significantly better then an SMT 4c/8t design.

[moshpit]

In fact, I'd be tempted to say a theoretical 8 core Phenom II of equal clock speed and cache type would whoop it up on a A8 series in CPU heavy multithreaded scenarios.

[caveman-jim]

In a 'normal' core you can do int or FP. When FP is running you can't do int, and vice versa. BD module gives you FP decoupled from Int - you can run 2 128-bit FP, attached to each Int core indivudually, or the whole 256-bit FP can be running for one Int core.

So for normal workloads it's dual core. For heavy FP it's dual core. For 256-bit it's single core, switching between two Int cores.

Dual core module.

[moshpit]

Originally Posted by caveman-jim

In a 'normal' core you can do int or FP. When FP is running you can't do int, and vice versa. BD module gives you FP decoupled from Int - you can run 2 128-bit FP, attached to each Int core indivudually, or the whole 256-bit FP can be running for one Int core.

So for normal workloads it's dual core. For heavy FP it's dual core. For 256-bit it's single core, switching between two Int cores.

Dual core module.

But once again, that's assuming a full set of resources for each core, which it doesn't have, hence the "1.8" reference above. There is some latency in this approach versus "dual core" as it's a step between SMT and SMP with some resources being shared between the units. By the reasoning AMD is using, Intel's core with HT could be called "dual core" if shared resources are not the determining factor. Ars makes VERY good points about this NOT being true dual core per module. In fact, they quite correctly, I believe, compare AMD's approach here to being somewhere between true dual core per module and Intel's HT.

Example question: Does each unit have it's own L1 and L2, or does it only have L1, and the L2 is shared between the units? And where else are resources shared?

[caveman-jim]

Shared components, as from link posted above.

HT works by using bubbles in the instruction pipeline, it cannot be considered dual core as there are no duplicated hardware. BD shares L2 between Int cores and the FP unit, but not L1 although whichever core needs the FP uses its L1 to the FP.

[moshpit]

Fetch, decode and L2 cache, those are some pretty big shared resources, it's not like AMD is generous with that L2 to begin with. I don't see it operating at the same speed as two full cores would, a lot closer then HT can achieve maybe, but still not a perfect 2x. I think Ars nailed this one with the "1.8" reference.

[moshpit]

Originally Posted by caveman-jim

Shared components, as from link posted above.

HT works by using bubbles in the instruction pipeline, it cannot be considered dual core as there are no duplicated hardware. BD shares L2 between Int cores and the FP unit, but not L1 although whichever core needs the FP uses its L1 to the FP.

It's not completely true that HT has no dedicated hardware. In fact, each independent LOGICAL processor has it's own Advanced Programmable Interrupt Controller (APIC).
http://www.utdallas.edu/~edsha/paral...perThreads.pdf

[caveman-jim]

Originally Posted by moshpit

Fetch, decode and L2 cache, those are some pretty big shared resources, it's not like AMD is generous with that L2 to begin with. I don't see it operating at the same speed as two full cores would, a lot closer then HT can achieve maybe, but still not a perfect 2x. I think Ars nailed this one with the "1.8" reference.

Regardless of the shades of grey you want to paint the performance increase over a hypothetical single int/fp core module (which won't ever exist), it's a dual core module. you can naysay it as 1.8 or less than 2, it still is capable of running two independent integer and/or fp threads concurrently - which HT can't.

As far as hypothetical 1 core to 2 core in a module scaling goes, as you say that's going to be highly decode dependent and dispatch dependent. I think AMD is going to surprise a lot of people with this CPU release, both Llano and Bulldozer. Are they going to be 20% ahead of Sandy Bridge? Thats going to depend on what everyone can agree on as relevant benchmarks.

[moshpit]

Originally Posted by caveman-jim

Regardless of the shades of grey you want to paint the performance increase over a hypothetical single int/fp core module (which won't ever exist), it's a dual core module. you can naysay it as 1.8 or less than 2, it still is capable of running two independent integer and/or fp threads concurrently - which HT can't.

As far as hypothetical 1 core to 2 core in a module scaling goes, as you say that's going to be highly decode dependent and dispatch dependent. I think AMD is going to surprise a lot of people with this CPU release, both Llano and Bulldozer. Are they going to be 20% ahead of Sandy Bridge? Thats going to depend on what everyone can agree on as relevant benchmarks.

Ummm, cavey, I'm SURE you know what SMT means. To say HT doesn't execute two concurrent threads in the EXACT way you just described is not true. I just clearly linked Intel material saying it does exactly that. I don't think you need me to teach you what SMT means. HT accomplishes 1.2 average, while CMP only does 1.8 at best guess for best case, your trying to make BD into something it's not. A SMP per module design, which it clearly is NOT since resources are still being shared. It is SMT/SMP hybrid, clearly. It's better then HT, but it's NOT a full second core within each module. I know you will NOT deny HT is a full SMT implementation.

I hate to say this, but you're the one saying gray isn't gray, both these techs are the gray area between one and two REAL cores, one is just a darker shade of gray is all. HT and CMP are NOT SMP. And your own linked chart clearly shows the units within each module are not full cores but even have to share a VERY small L2 cache, among other things as well. That is NOT two full cores in ANYBODY'S book.

[seeker010]

Originally Posted by caveman-jim

It can execute 2 int threads and 2 fp threads in each module, hence it is a dual core. What is different is being able to combine the fp to work on one thread for more throughput for an fp intensive task instead of leaving 1 fp idle.

Read more here.

Yes, but each K10 FPU core has a FADD unit and a FMUL unit and a FMISC unit. in tasks with FMUL/FADD parallelism, BD isn't going to do much better. Now on FPU tasks that can't be pipelined (like FDIV, FSQRT), BD will offer the advantage since it looks like the two units are symmetrical so you can do 2 FDIVS concurrently.

[Sasquach]

IF i was to make an analogy of this BD core situation, would it be similar to conjoined twins? Is that considered 2 people or 1?
And HT is more like one person with 2 heads.

[seeker010]

Originally Posted by Sasquach

IF i was to make an analogy of this BD core situation, would it be similar to conjoined twins? Is that considered 2 people or 1?
And HT is more like one person with 2 heads.

1.5? like 2 bodies sharing the same heart and stomach.

[Crisler]

I think the point here is to not let the marketting hype get in the way. This is NOT in anyway a true dual core system, it is more of an advanced Hybrid. Is it closed than HT, yes by a good margian but at the same time it is not the equivelent in core functionality of a real dual core. The shared resources make it fall short.

However at the end of the day none of that matters. What does matter is what it delivers. I could have one core with a monkey tail and if it gave me great performance at a great price it would be a good chip.

Forget the hype on both ends and lets hold until the real chips are in our greedy little hands.

[moshpit]

Originally Posted by Sasquach

IF i was to make an analogy of this BD core situation, would it be similar to conjoined twins? Is that considered 2 people or 1?
And HT is more like one person with 2 heads.

In fact, this IS an apt analogy. If the point is to carry on 2 conversations, the performance won't be the same, but the effect will be. 2 threads per core in flight at any one time. Yes, BD will do a better job of it, but it still won't be perfect and expecting to be a true dual core per module is setting oneself up for let down. Hype is a dangerous thing.