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Old Aug 11, 2010, 10:33 AM   #1
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erek
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Intel Intel unveils Knights Ferry HPC Co-Processor specifications

32 cores, 128 threads, 8MB shared L2 cache, 1.20GHz

Earlier this week, Intel VP Kirk Skaugen released a PowerPoint slide detailing the rich history of Intel’s commitment to HPC innovation, its progression from the Petascale age to the Exascale age of supercomputing, and some hard specifications for its highly parallelized MIC architecture aimed at enterprise markets.

Back in 2007, we wrote that Larrabee was initially designed as a discrete graphics engine and was also capable of computing highly parallel applications while preserving x86 programmability. In May 2010, Bill Kircos, Intel’s Director of Product and Technology Media Relations, announced that the Larrabee project would never materialize as a discreet GPU part and would instead be transitioned into a new architecture leveraging both Larrabee and Intel’s many core research projects.

During ISC 2010, that architecture soon came to be known to the HPC crowd as Intel MIC (Many Integrated Core). In its official announcement, Intel outlined plans to ship a MIC development kit platform to select customers known as Knights Ferry. According to Slide 34 of Skaugen’s keynote presentation, Knights Ferry is an x86-based design with 32 cores on a single chip, each with four threads, a 32KB L1 instruction cache, a 32KB L1 data cache, and a 256KB L2 cache. In total, the chip has 8MB of shared L2 cache, which some analysts note to be an interesting design point as many high-parallel applications do not require such a large on-chip cache.


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