Company: AMD
Authour: James Prior
Editor: Charles Oliver
Date: December 6th, 2010
Both AMD and Intel have disclosed details of their new micro architectures launching in 1H 2011. AMD's Bobcat based design is due now (Q4 2010 - Q1 2011), and Bulldozer is due in Q2 2011. Bobcat will be featured initially in ultra-portable notebooks and later in mainstream notebooks and desktops, as FUSION Accelerated Processing Units (APU); Bulldozer will be the performance desktop part.
Intel's Sandy Bridge micro architecture is due Q1 2011 and will be featured in both performance desktop and mainstream desktop parts. Both companies will likely have announcements at CES 2011, with Intel launching Sandy Bridge on January 5th. Bulldozer and Sandy Bridge based products will require new sockets - 1155 for Intel, and AM3+ for AMD. AM3+ will be backwards compatible with AM3 processors - you'll be able to upgrade just the mainboard without replacing the CPU as well, offering a smooth piecemeal transition.
Thuban

AMD
![]() Thuban Die |
AMD uses HyperTransport to connect their processors to the rest of the system. The Phenom II X6 series processors support HT 3.0, running a single 16-bit/16-bit link at 2.0GHz. The CPU integrated memory controller offers two modes of operation, ganged and unganged. This refers to how the memory channels are grouped, and really only needs to be considered when populating all four memory slots. Ganged mode is equivalent to the old dual-channel mode, where both 64-bit memory buses are combined to make a single 128-bit bus for improved memory bandwidth. However, unganged mode offers simultaneous read/write operations to different banks - reducing latency for systems performing heavy multi-tasking. This requires all four memory slots to be populated.
The Thuban core itself measures ~346mm2, with approximately 904m transistors. Thuban is manufactured on GLOBALFOUNDRIES 45nm SOI process in Germany, and has a maximum TDP of 125W. The turbo mode is made possible through monitoring the power use of the processor, and placing unused cores into sleep states. This additional room in the 'power envelope' can be claimed back by increasing the clock speed of the remaining active cores - 3, by default. Clock speed is boosted up to 500MHz. AMD Overdrive software allows the user to adjust clock speeds, by multiplier in the case of Black Edition processors, as well as by base clock. You can also configure the Turbo Core mode - the number of turbo cores to use, which turbo cores to use, and per core turbo settings. If you want to run on the ragged edge for each core, this is the app for that.
Bloomfield

Intel
SMT can boost performance in multi-threaded applications by switching execution contexts - two different processing threads executing simultaneously on the same hardware by using the natural gaps in the instruction pipe. Filling these 'bubbles' allows the processor to perform more work in the same time, and by leveraging the Out-Of-Order architecture inherent to Nehalem, allows for significant performance throughput increases for some workloads. Rarely, it can add time to currently executing threads, causing latency increases and inconsistent execution times, and individual core cache sharing between threads can impact speed. Due to the nature of SMT, the design is considered a quad core processor, despite the 8 threads available in Windows and other SMP capable OS kernels.
![]() Bloomfield Die |
Famously, Bloomfield introduced triple-channel memory support, officially up to DDR3-1066. This significantly increased memory bandwidth, and made for some interesting board designs to accommodate the new possible configurations with six DIMMs. Several factors including the power state support and uncore/core design meant a new socket for the high performance desktop parts, using X58 chipset and LGA socket 1366. X58 removed the legacy and restrictive front-side bus (FSB) design, introducing Quick Path Interconnect (QPI) for communication between the CPU and other devices. At 4.6GT/s (Giga-transfers per second) there was no longer a bottleneck between the system and CPU as previously found with the FSB design.
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